1. Field of the Disclosure
Generally, the present disclosure relates to semiconductor devices, and, more particularly, to a novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure.
2. Description of the Related Art
A multitude of semiconductor devices are typically fabricated on a single semiconductor wafer substrate. Following a fabrication process sequence, individual devices or “die” are typically separated or “diced” from the substrate by sawing or laser scribing. These die are then incorporated within a packaging structure generally designed to seal the active area of the die and electrically connect the device terminals with those of an external circuit. Depending on the type of chip and the overall device design requirements, these electrical connections may be accomplished in a variety of ways, such as, for example, by wire bonding, tape automated bonding (TAB), flip-chip bonding and the like. In recent years, the use of flip-chip technology, wherein semiconductor chips are attached to carrier substrates, or to other chips, by means of solder balls formed from so-called solder bumps, has become an important aspect of the semiconductor processing industry. In flip-chip technology, solder balls are formed on a contact layer of at least one of the chips that is to be connected, such as, for example, on a dielectric passivation layer formed above the last metallization layer of a semiconductor chip comprising a plurality of integrated circuits. Similarly, adequately sized and appropriately located bond pads are formed on another chip, such as, for example, a carrier package, each of which corresponds to a respective solder ball formed on the semiconductor chip. The two units, i.e., the semiconductor chip and carrier substrate, are then electrically connected by “flipping” the semiconductor chip and bringing the solder balls into physical contact with the bond pads, and performing a “reflow” process so that each solder ball bonds to a corresponding bond pad. Typically, hundreds of solder bumps may be distributed over the entire chip area, thereby providing, for example, the I/O capability required for modern semiconductor chips that usually include complex circuitry, such as microprocessors, storage circuits, three-dimensional (3D) chips and the like, and/or a plurality of integrated circuits forming a complete complex circuit system.
When devices are packaged using flip-chip bonding, solder beads or “bumps” often made of lead (Pb) or a lead alloy are reflowed and used to connect conductive terminals on the device to metal leads within the package. The active side of the device including the soldered interconnects is then encapsulated by an under-filling sealant that, when cured, provides an environmentally resistant barrier. However, there is an ongoing effort by semiconductor device manufacturers to eliminate the use of many potentially hazardous materials, including lead. Accordingly, other electrically conductive materials, such as copper and copper alloys, have been studied as potential replacements for lead-based solder interconnects. While copper interconnects have high electrical conductivity and improved mechanical strength compared with lead-based solders, copper is less ductile and thus is less able to absorb stress. As a result, shearing stresses between the packaging substrate and the surface of the die are often transferred by the relatively rigid copper interconnect to more brittle, back end of line (BEOL) and/or passivation layers within the die. Such stresses may be caused by, for example, a mismatch in the coefficient of thermal expansion (CTE) between the die and the packaging substrate, and can potentially fracture BEOL/passivation layers, causing device failure. Therefore, an interconnecting structure capable of providing greater stress relief is desirable to prevent fracture of BEOL/passivation layers and improve the reliability of such devices.
FIGS. 1A-1B depict an illustrative prior art integrated circuit device 10 comprised of an illustrative prior art copper pillar 24 that may be used in packaging integrated circuit devices. In general, the device 10 comprises a substrate 12, where integrated circuits are formed, a schematically depicted and so-called back-end-of-line (BEOL) stack 14. The BEOL stack 14 typically contains a plurality of metallization layers positioned in numerous layers of insulating material. The metallization layers contain conductive lines and vias that constitute the “wiring” for the integrated circuits that are formed in and above the substrate 12.
With continuing reference to FIG. 1A, the device 10 typically includes a lower passivation layer 16, a conductive bond pad 17, e.g., an aluminum bond pad, an upper passivation layer 18, a polyimide layer 20, a so-called under-bump metallization (UBM) layer 22, the copper pillar 24, a layer of metal 26, such as nickel, and a tin-silver bump 28. The manner in which such structures are formed are well known to those skilled in the art. Importantly, as shown in FIGS. 1A-1B, the copper pillar 24 has a substantially uniform shape and configuration along its entire vertical axis or length. In the depicted example, the copper pillar 24 has a substantially cylindrical configuration. While the substantially cylindrical copper pillar 24 may be relatively easy to fabricate, such a large and rigid structure may lead to stress-related problems such as those mentioned above. Accordingly, it would be desirable to have a pillar structure that is less rigid than the prior art copper pillar depicted in FIGS. 1A-1B and thus more useful as a conductive structure for use in packaging integrated circuit products.
The present disclosure relates to novel pillar structure for use in packaging integrated circuit products that may avoid, or at least reduce, the effects of one or more of the problems identified above.